1. Field of the Invention
This disclosure relates to a semiconductor device and a manufacturing method thereof. This disclosure in particular relates to a semiconductor device with epitaxial source/drain extension regions and a manufacturing method thereof.
2. Description of the Related Art
Nowadays, millions of semiconductor devices are integrated together to form very large scale integrated circuits.
FIG. 1 shows a sectional view of a conventional semiconductor device (transistor). The transistor generally comprises a gate dielectric layer 140 on a semiconductor substrate and a gate layer 150 on the gate dielectric layer 140. Sidewall spacers 160 and 165 are formed on sidewalls of the gate dielectric layer 140 and the gate layer 150. The transistor generally also comprises a pair of source/drain regions 110 on opposing sides of the gate layer 150. In addition, a pair of source/drain extension regions 120 is formed in the surface region of the semiconductor substrate, and extends beneath the gate dielectric layer 140 and the gate layer 150. A channel region 130 is formed in the semiconductor substrate between the pair of source/drain extension regions 120 and beneath the gate dielectric layer 140.
With the continuous shrink of the critical size of the transistor, it is desired for the source/drain extension regions 120 to have a shallow junction depth (or a small thickness) so as to reduce the area junction capacitance, and it is also desired for the source/drain extension regions 120 to have a high activated dopant concentration so as to reduce the accumulation resistance, thereby the driving current of the transistor is increased.
For the above purposes, annealing, especially laser melting/sub-melting annealing, is generally applied to the source/drain extension regions formed by ion implantation.
However, the present inventor has conducted in-depth investigation on this, and has found that further improvement is still expected on the junction depth and activated dopant concentration of the source/drain extension regions formed by ion implantation and laser melting/sub-melting annealing. Incidentally, although SIMS (Secondary Ion Mass Spectrometry) is generally used to measure dopant profiles after laser melting/sub-melting annealing, SIMS is unable to distinguish whether dopants are activated or not.
Therefore, the present inventor has recognized that there is a need for a semiconductor device, which has source/drain extension regions with a shallow junction depth (or a small thickness) and a high activated dopant concentration, and a manufacturing method thereof.